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cy7c1021d 1-mbit (64k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05462 rev. *e revised february 22, 2007 features ? pin-and function-compatible with cy7c1021b ? high speed ?t aa = 10 ns ? low active power ?i cc = 80 ma @ 10 ns ? low cmos standby power ?i sb2 = 3 ma ? 2.0v data retention ? automatic power-down when deselected ? cmos for optimum speed/power ? independent control of upper and lower bits ? available in pb-free 44-pin 400-mil wide molded soj and 44-pin tsop ii packages functional description [1] the cy7c1021d is a high-perf ormance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselec ted. the input/output pins (io 0 through io 15 ) are placed in a high-impedance state when: ? deselected (ce high) ? outputs are disabled (oe high) ?bhe and ble are disabled (bhe , ble high) ? when the write operation is active (ce low, and we low) write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 15 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 8 for a complete description of read and write modes. logic block diagram 64k x 16 ram array io 0 ?io 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 io 8 ?io 15 ce we ble bhe a 8 note 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress a pplication note, available on t he internet at www.cypress.com . [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 2 of 11 pin configuration [2] selection guide ?10 (industrial) ?12 (automotive) [3] unit maximum access time 10 12 ns maximum operating current 80 120 ma maximum cmos standby current 3 15 ma 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 soj/tsop ii top view a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc nc oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 notes 2. nc pins are not connected on the die. 3. automotive product information is preliminary. [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 3 of 11 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [4] ... ?0.5v to +6.0v dc voltage applied to outputs in high-z state [4] .....................................?0.5v to v cc +0.5v dc input voltage [4] ..................................?0.5v to v cc +0.5v current into outputs (low) ........................................ 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40c to +85c 5v 10% 10 ns automotive ?40c to +125c 12 ns electrical characteristics (over the operating range) parameter description test conditions ?10 (industrial) ?12 (automotive) unit min max min max v oh output high voltage i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5v 2.0 v cc + 0.5v v v il input low voltage [4] ? 0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ? 1+1 ?5 +5 a i oz output leakage current gnd < v i < v cc , output disabled ? 1+1 ?5 +5 a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz 80 -ma 83 mhz 72 120 ma 66 mhz 58 100 ma 40 mhz 37 63 ma i sb1 automatic ce power-down current ?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max 10 50 ma i sb2 automatic ce power-down current ?cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 3 15 ma note 4. v il (min) = ?2.0v and v ih (max) = v cc + 1v for pulse durations of less than 5 ns. [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 4 of 11 capacitance [5] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8 pf c out output capacitance 8 pf thermal resistance [5] parameter description test conditions soj tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 59.52 53.91 c/w jc thermal resistance (junction to case) 36.75 21.24 c/w ac test loads and waveforms [6] 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 3 ns fall time: 3 ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 5v output 5 pf (c) r1 480 ? r2 255 ? high-z characteristics: including jig and scope notes 5. tested initially and after any design or proce ss changes that may affect these parameters. 6. ac characteristics (except high-z) are te sted using the load conditions shown in fi gure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 5 of 11 switching characteristics (over the operating range) [7] parameter description ?10 (industrial) ?12 (automotive) unit min max min max read cycle t power [8] v cc (typical) to the first access 100 100 s t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 10 12 ns t doe oe low to data valid 5 6ns t lzoe oe low to low z [9] 0 0 ns t hzoe oe high to high z [9, 10] 5 6ns t lzce ce low to low z [9] 3 3 ns t hzce ce high to high z [9, 10] 5 6ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 10 12 ns t dbe byte enable to data valid 5 6ns t lzbe byte enable to low z 0 0 ns t hzbe byte disable to high z 5 6ns write cycle [12] t wc write cycle time 10 12 ns t sce ce low to write end 7 10 ns t aw address set-up to write end 7 10 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 10 ns t sd data set-up to write end 6 7 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [9] 3 3 ns t hzwe we low to high z [9, 10] 5 6ns t bw byte enable to end of write 7 10 ns notes 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 8. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (c) of ?ac test loads and waveforms [6]? on page 4 . transition is measured when the outputs enter a high impedance state. 11. this parameter is guaranteed by design and is not tested. 12. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. th e input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 6 of 11 data retention characteristics (over the operating range) parameter description conditions min max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v industrial 3 ma automotive 15 ma t cdr [4] chip deselect to data retention time 0 ns t r [13] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 (address transition controlled) [14, 15] read cycle no. 2 (oe controlled) [15, 16] 4.5v 4.5v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current notes 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 s or stable at v cc(min) > 50 s. 14. device is continuously selected. oe , ce , bhe and/or ble = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 7 of 11 write cycle no. 1 (ce controlled) [17, 18] write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data io address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data io address bhe ,ble ce we notes 17. data io is high impedance if oe or bhe and/or ble = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 8 of 11 write cycle no. 3 (we controlled, oe low) truth table ce oe we ble bhe io 0 ?io 7 io 8 ?io 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1021D-10VXI 51-85082 44-pin (400-mil) molded soj (pb-free) industrial cy7c1021d-10zsxi 51-85087 44-pin tsop type ii (pb-free) 12 cy7c1021d-10zsxe 51-85087 44-pin tsop type ii (pb-free) automotive shaded areas contain advance information. please contact your loca l cypress sales representative for availability of these part s. switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data io address ce we bhe ,ble [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 9 of 11 package diagrams figure 1. 44-pin (400-mil) molded soj, 51-85082 51-85082-*b [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 10 of 11 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems wh ere a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. figure 2. 44-pin thin small outline package type ii, 51-85087 all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 51-85087-*a [+] feedback [+] feedback
cy7c1021d document #: 38-05462 rev. *e page 11 of 11 document history page document title: cy7c1021d, 1-mbit (64k x 16) static ram document number: 38-05462 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance information data sheet for c9 ipp *a 233695 see ecn rkf dc parameters modified as per eros (spec # 01-02165) pb-free offering in the ordering information *b 263769 see ecn rkf added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307601 see ecn rkf reduced speed bins to ?10 and ?12 ns *d 520647 see ecn vkn converted from preliminary to final removed commercial operating range added i cc values for the frequencies 83mhz, 66mhz and 40mhz updated thermal resistance table added automotive pr oduct information updated ordering information table changed overshoot spec from v cc +2v to v cc +1v in footnote #4 *e 802877 see ecn vkn changed commercial operating range i cc spec from 60 ma to 80 ma for 100mhz, 55 ma to 72 ma for 83mhz, 45 ma to 58 ma for 66mhz, 30 ma to 37 ma for 40mhz changed automotive operating range i cc spec from 100 ma to 120 ma for 83mhz, 90 ma to 100 ma for 66m hz, 60 ma to 63 ma for 40mhz [+] feedback [+] feedback

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